View GS8662D08E-XXX_4507040.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary gs8662d08/09/18/36e -333/300/250/200/167 72mb sigmaquad-ii burst of 4 sram 333 mhz?167 mhz 1.8 v v dd 1.8 v and 1.5 v i/o 165-bump bga commercial temp industrial temp rev: 1.01a 2/2006 1/29 ? 2005, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? simultaneous read and write sigmaquad? interface ? jedec-standard pinout and package ? dual double data rate interface ? byte write controls sampled at data-in time ? burst of 4 read and write ? 1.8 v +100/?100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq pin for programmable output drive strength ? ieee 1149.1 jtag-compliant boundary scan ? pin-compatible with present 9mb, 18mb, and 36mb and future 144mb devices ? 165-bump, 15 mm x 17 mm, 1 mm bump pitch bga package ? rohs-compliant 165-bump bga package available sigmaquad ? family overview the gs8662d08/09/18/36e are built in compliance with the sigmaquad-ii sram pinout standard for separate i/o synchronous srams. they are 75,497,472-bit (72mb) srams. the gs8662d08/18/36e sigmaquad srams are just one element in a family of low power, low voltage hstl i/o srams designed to operat e at the speeds needed to implement economical high perf ormance networking systems. clocking and addressing schemes the gs8662d08/09/18/36e sigmaquad-ii srams are synchronous devices. they employ two input register clock inputs, k and k . k and k are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. the device also allows the user to manipulate the output register clock inputs quasi independently with the c and c clock inputs. c and c are also independent single-ended clock inputs, not differential inputs. if the c clocks are tied high, the k clocks are routed internally to fire the output registers instead. because separate i/o sigmaquad-ii b4 rams always transfer data in four packets, a0 and a1 are internally set to 0 for the first read or write transfer, an d automatically incremented by 1 for the next transfers. because the lsbs are tied off internally, the address field of a sigmaquad-ii b4 ram is always two address pins less than the advertised index depth (e.g., the 4m x 18 has a 1024k addressable index). parameter synopsis - 333 -300 -250 -200 -167 tkhkh 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tkhqv 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.50 ns 165-bump, 15 mm x 17 mm bga 1 mm bump pitch, 11 x 15 bump array bottom view
2m x 36 sigmaqua d-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq mcl/sa (288mb) sa w bw2 k bw1 r sa mcl/sa (144mb) cq b q27 q18 d18 sa bw3 k bw0 sa d17 q17 q8 c d27 q28 d19 v ss sa nc sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa c sa sa q9 d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to d0:d8; bw1 controls writes to d9:d17; bw2 controls writes to d18:d26; bw3 controls writes to d27:d35 2. mcl = must connect low preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 2/29 ? 2005, gsi technology
4m x 18 sigmaqua d-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq mcl/sa (144mb) sa w bw1 k nc r sa sa cq b nc q9 d9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa nc sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. 2. mcl = must connect low preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 3/29 ? 2005, gsi technology
8m x 9 sigmaquad-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w nc k nc r sa sa cq b nc nc nc sa nc k bw0 sa nc nc q4 c nc nc nc v ss sa nc sa v ss nc nc d4 d nc d5 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q5 v ddq v ss v ss v ss v ddq nc d3 q3 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d6 q6 v ddq v dd v ss v dd v ddq nc nc nc h d off v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q2 d2 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q7 d7 v ddq v ss v ss v ss v ddq nc nc q1 m nc nc nc v ss v ss v ss v ss v ss nc nc d1 n nc d8 nc v ss sa sa sa v ss nc nc nc p nc nc q8 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to d0:d8. 2. mcl = must connect low preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 4/29 ? 2005, gsi technology
8m x 8 sigmaquad-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w nw1 k nc r sa sa cq b nc nc nc sa nc k nw0 sa nc nc q3 c nc nc nc v ss sa nc sa v ss nc nc d3 d nc d4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q4 v ddq v ss v ss v ss v ddq nc d2 q2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d5 q5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q1 d1 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q6 d6 v ddq v ss v ss v ss v ddq nc nc q0 m nc nc nc v ss v ss v ss v ss v ss nc nc d0 n nc d7 nc v ss sa sa sa v ss nc nc nc p nc nc q7 sa sa c sa sa nc nc nc r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch notes: 1. nw0 controls writes to d0:d3. nw1 controls writes to d4:d7. 2. mcl = must connect low preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 5/29 ? 2005, gsi technology
pin description table symbol description type comments sa synchronous address inputs input ? nc no connect ? ? r synchronous read input active low w synchronous write input active low bw0 ? bw3 synchronous byte writes input active low x9/x18/x36 only nw0 ? nw1 nybble write control pin input active low x8 only k input clock input active high k input clock input active low c output clock input active high c output clock input active low tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? qn synchronous data outputs output dn synchronous data inputs input d off disable dll when low input active low cq output echo clock output ? cq output echo clock output ? v dd power supply supply 1.8 v nominal v ddq isolated output buffer supply supply 1.5 or 1.8 v nominal v ss power supply: ground supply ? preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 6/29 ? 2005, gsi technology note: nc = not connected to die or any other pin
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 7/29 ? 2005, gsi technology background separate i/o srams, from a syst em architecture point of view, are attractive in applications where alte rnating reads and writes are needed. therefore, the sigmaquad- ii sram interface and truth table are optimized for alternating reads a nd writes. separate i/o srams are unpopular in app lications where multiple reads or multiple writes are needed because burst read or write transfers fr om separate i/o srams can cut the ram?s bandwidth in half. alternating read-write operations sigmaquad-ii srams follow a few simple rules of operation. - read or write commands issued on one po rt are never allowed to interrupt an operation in progress on the other port. - read or write data transfers in progres s may not be interrupted and re-started. - r and w high always deselects the ram. - all address, data, and control inputs are sampled on clock edges. in order to enforce these rules, each ram combines present st ate information with command i nputs. see the truth table for details. sigmaquad-ii b4 sram ddr read the status of the address input, w , and r pins are sampled by the rising edges of k. w and r high causes chip disable. a low on the read enable-bar pin, r , begins a read cycle. r is always ignored if the previous co mmand loaded was a read command. data can be clocked out after the next rising edge of k with a rising edge of c (or by k if c and c are tied high), after the following rising edge of k with a rising edge of c (or by k if c and c are tied high), after the next rising edge of k with a rising edge of c , and after the following rising edge of k with a rising edge of c. clocking in a high on the read enable-bar pin, r , begins a read port deselect cycle. sigmaquad-ii b4 double data rate sram read first read a nop read b write c read d write e nop a b c d e c c+1 c+2 c+3 e e+1 c c+1 c+2 c+3 e e+1 a a+1 a+2 a+3 b b+1 b+2 b+3 d d+1 d+ 2 k k address r w bwx d c c q cq cq
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 8/29 ? 2005, gsi technology sigmaquad-ii b4 sram ddr write the status of the address input, w , and r pins are sampled by the rising edges of k. w and r high causes chip disable. a low on the write enable-bar pin, w , and a high on the read enable-bar pin, r , begins a write cycle. w is always ignored if the previous command was a write command. data is clocked in by the next rising edge of k, the rising edge of k after that, the next rising edge of k, and finally by the next rising edge of k . and by the rising edge of the k that follows. sigmaquad-ii b4 double data rate sram write first write a nop read b write c read d write e nop a b c d e a a+1 a+2 a+3 c c+1 c+2 c+3 e e+1 e + a a+1 a+2 a+3 c c+1 c+2 c+3 e e+1 e + b b+1 b+2 b+3 d d+1 d+2 k k address r w bwx d c c q cq cq
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 9/29 ? 2005, gsi technology power-up sequence fo r sigmaquad-ii srams sigmaquad-ii srams must be powered-up in a specifi c sequence in order to avoid undefined operations. power-up sequence 1. power-up and maintain doff at low state. 1a. apply v dd . 1b. apply v ddq . 1c. apply v ref (may also be applied at the same time as v ddq ). 2. after power is achieved and clocks (k, k , c, c ) are stablized, change doff to high. 3. an additional 1024 clock cycl es are required to lock the dll after it has been enabled. note: if you want to tie doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the dll after the clocks become stablized. dll constraints ? the dll synchronizes to either k or c clock. these clocks should have low phase jitter (t kcvar on page 21 ). ? the dll cannot operate at a frequency lower than 119 mhz. ? if the incoming clock is not stablized when dll is enabled, the dll may lock on th e wrong frequency and cause undefined errors or failures during the initial stage. power-up sequence ( doff controlled) power up interval unstable clocking interval dll locking interval (1024 cycles) normal operation k k v dd v ddq v ref doff power-up sequence ( doff tied high) power up interval unstable clocking interval stop clock interval dll locking interval (1024 cycles) normal operation k k v dd v ddq v ref doff 30ns min note: if the frequency is changed, dll reset is required. after reset, a minimum of 1024 cycles is required for dll lock.
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 10/29 ? 2005, gsi technology special functions byte write and nybble write control byte write enable pins are sampled at the same time that data in is sampled. a high on the byte write enable pin associated wit h a particular byte (e.g., bw0 controls d0?d8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. a ny or all of the byte write enable pins may be driven high or low during the data in sample times in a write sequence. each write enable command and write addres s loaded into the ram provides the base ad dress for a 4 beat data transfer. the x18 version of the ram, for example, may write 72 bits in associatio n with each address loaded. any 9-bit byte may be masked in any write sequence. nybble write (4-bit) control is implemented on the 8-bit-wide version of the device. for the x8 version of the device, ?nybble write enable? and ? nbx ? may be substituted in all the discussion above. example x18 ram write sequence using byte write enables data in sample time bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in beat 3 0 0 data in data in beat 4 1 0 don?t care data in resulting write operation byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 written unchanged unchanged written written written unchanged written beat 1 beat 2 beat 3 beat 4 output register control sigmaquad-ii srams offer two mechanisms for controlling the output data registers. typically, control is handled by the output register clock inputs, c and c . the output register clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of th e k and k clocks. if the c and c clock inputs are tied high, the ram reverts to k and k control of the outputs, allowing the ram to function as a conventional pipelined read sram.
a k r w a 0 ?a n k w 0 d 1 ?d n bank 0 bank 1 bank 2 bank 3 r 0 d a k w d a k w d a k w d r r r qqq q cc cc q 1 ?q n c w 1 r 1 w 2 r 2 w 3 r 3 note: for simplicity bwn , nwn , k , and c are not shown. cq cq cq cq cq 0 cq 1 cq 2 cq 3 preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 11/29 ? 2005, gsi technology example four bank depth expansion schematic
2x2b4 sigmaquad-ii s ram depth expansion read a write b read c write d read e write f nop a b c d e f d d+1 d+2 d+3 d d+1 d+2 d+3 b b+1 b+2 b+3 f f+1 f b b+1 b+2 b+3 f f+1 f a a+1 a+2 a+3 e e+1 e+ 2 c c+1 c+2 c+3 k k address r (1) r (2) w (1) w (2) bwx (1) d(1) bwx (2) d(2) c[1] c [1] q(1) cq(1) cq [1] c[2] c [2] q(2) cq[2] cq [2] preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 12/29 ? 2005, gsi technology
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 13/29 ? 2005, gsi technology flxdrive-ii output driver impedance control hstl i/o sigmaquad-ii srams are supplied with programmable impedance output drivers. the zq pin must be connected to v ss via an external resistor, rq, to allow th e sram to monitor and adjust its output driver impedance. the value of rq must be 5x the value of the desired ram output impedance. the allowable range of rq to guarantee impeda nce matching continuously is between 150 ? and 300 ? . periodic readjustment of the output driver impedance is necessary as th e impedance is affected by drifts in supply voltage and temperature. the sram?s output impeda nce circuitry compensates for drifts in supply voltage and temperature. a clock cycle counter periodically triggers an impedance evaluation, resets and counts again. each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. the output driver is implemented with discrete binary weighted impedance steps. updates of pull-down drive impedan ce occur whenever a driver is producing a ?1? or is high-z. pull-up drive impedance is updated when a driver is producing a ?0? or is high-z. separate i/o sigmaquad-ii b4 sram truth table previous operation a r w current operation d d d d q q q q k (t n-1 ) k (t n ) k (t n ) k (t n ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) deselect x 1 1 deselect x x ? ? hi-z hi-z ? ? write x 1 x deselect d2 d3 ? ? hi-z hi-z ? ? read x x 1 deselect x x ? ? q2 q3 ? ? deselect v 1 0 write d0 d1 d2 d3 hi-z hi-z ? ? deselect v 0 x read x x ? ? q0 q1 q2 q3 read v x 0 write d0 d1 d2 d3 q2 q3 ? ? write v 0 x read d2 d3 ? ? q0 q1 q2 q3 notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?v ? = input ?valid?; ?x? = input ?don?t care? 2. ??? indicates that the input requirement or output state is determined by the next operation. 3. q0, q1, q2, and q3 indicate the first, second, third, and f ourth pieces of output data transferred during read operations. 4. d0, d1, d2, and d3 indicate the first, second, third, and four th pieces of input data tran sferred during write operations. 5. qs are tristated for one cycle in response to deselect and writ e commands, one cycle after the command is sampled, except whe n pre - ceded by a read command. 6. users should not clock in metastable addresses.
byte write clock truth table bw bw bw bw current operation d d d d k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) t t t t write dx stored if bwn = 0 in all four data transfers d0 d2 d3 d4 t f f f write dx stored if bwn = 0 in 1st data transfer only d0 x x x f t f f write dx stored if bwn = 0 in 2nd data transfer only x d1 x x f f t f write dx stored if bwn = 0 in 3rd data transfer only x x d2 x f f f t write dx stored if bwn = 0 in 4th data transfer only x x x d3 f f f f write abort no dx stored in any of the four data transfers x x x x notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more bwn = 0, then bw = ?t?, else bw = ?f?. preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 14/29 ? 2005, gsi technology
x36 byte write enable ( bwn ) truth table bw0 bw1 bw2 bw3 d0?d8 d9?d17 d18?d26 d27?d35 1 1 1 1 don?t care don?t care don?t care don?t care 0 1 1 1 data in don?t care don?t care don?t care 1 0 1 1 don?t care data in don?t care don?t care 0 0 1 1 data in data in don?t care don?t care 1 1 0 1 don?t care don?t care data in don?t care 0 1 0 1 data in don?t care data in don?t care 1 0 0 1 don?t care data in data in don?t care 0 0 0 1 data in data in data in don?t care 1 1 1 0 don?t care don?t care don?t care data in 0 1 1 0 data in don?t care don?t care data in 1 0 1 0 don?t care data in don?t care data in 0 0 1 0 data in data in don?t care data in 1 1 0 0 don?t care don?t care data in data in 0 1 0 0 data in don?t care data in data in 1 0 0 0 don?t care data in data in data in 0 0 0 0 data in data in data in data in x18 byte write enable ( bwn ) truth table bw0 bw1 d0?d8 d9?d17 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in x09 byte write enable ( bwn ) truth table bw0 d0?d8 1 don?t care 0 data in 1 don?t care 0 data in preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 15/29 ? 2005, gsi technology
nybble write cl ock truth table nw nw nw nw current operation d d d d k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) t t t t write dx stored if nwn = 0 in all four data transfers d0 d2 d3 d4 t f f f write dx stored if nwn = 0 in 1st data transfer only d0 x x x f t f f write dx stored if nwn = 0 in 2nd data transfer only x d1 x x f f t f write dx stored if nwn = 0 in 3rd data transfer only x x d2 x f f f t write dx stored if nwn = 0 in 4th data transfer only x x x d3 f f f f write abort no dx stored in any of the four data transfers x x x x notes : 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more nwn = 0, then nw = ?t?, else nw = ?f?. x8 nybble write enable ( nwn ) truth table nw0 nw1 d0?d3 d4?d7 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 16/29 ? 2005, gsi technology
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 17/29 ? 2005, gsi technology state diagram power-up read nop load new read address d count = 0 ddr read d count = d count + 1 write nop load new write address d count = 0 ddr write d count = d count + 1 write read read d count = 2 write d count = 2 read write always always read d count = 2 notes: 1. internal burst counter is fixed as 2- bit linear (i.e., when first address is a0 +0, next internal burst address is a0+1. 2. ?read? refers to read active status with r = low, ?read ? refers to read inactive status with r = high. the same is true for ?write? and ?write ?. 3. read and write state machine can be active simultaneously. 4. state machine control timi ng sequence is controlled by k. read d count = 1 always increment read address write d count = 2 increment write address write d count = 1 always
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.9 v v ddq voltage in v ddq pins ?0.5 to v dd v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 2.9 v max.) v v in voltage on other input pins ?0.5 to v ddq +0.5 ( 2.9 v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be restricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component. preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 18/29 ? 2005, gsi technology recommended oper ating conditions power supplies parameter symbol min. typ. max. unit supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v ddq 1.4 1.5 v dd v reference voltage v ref 0.68 ? 0.95 v notes: 1. the power supplies need to be powered up si multaneously or in the following sequence: v dd , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . 2. most speed grades and configurations of this device are offered in both commerc ial and industrial temperature ranges. the part number of industrial temperature range versions end the character ?i?. unless other wise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. operating temperature parameter symbol min. typ. max. unit ambient temperature (commercial range versions) t a 0 25 70 c ambient temperature (industrial range versions) t a ?40 25 85 c
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 19/29 ? 2005, gsi technology hstl i/o dc input characteristics parameter symbol min max units notes dc input logic high v ih (dc) v ref + 0.1 v dd + 0.3 v 1 dc input logic low v il (dc) ?0.3 v ref ? 0.1 v 1 notes: 1. compatible with both 1.8 v and 1.5 v i/o drivers 2. these are dc test criteria . dc design criteria is v ref 50 mv. the ac v ih /v il levels are defined separatel y for measuring timing param - eters. 3. v il (min)dc = ?0.3 v, v il (min)ac = ?1.5 v (pulse width 3 ns). 4. v ih (max)dc = v ddq + 0.3 v, v ih (max)ac = v ddq + 0.85 v (pulse width 3 ns). hstl i/o ac input characteristics parameter symbol min max units notes ac input logic high v ih (ac) v ref + 200 ? mv 3,4 ac input logic low v il (ac) ? v ref ? 200 mv 3,4 v ref peak to peak ac voltage v ref (ac) ? 5% v ref (dc) mv 1 notes: 1. the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. to guarantee ac characteristics, v ih ,v il , trise, and tfall of inputs and clocks must be within 10% of each other. 3. for devices supplied with hstl i/o input buffers . compatible with both 1.8 v and 1.5 v i/o drivers. 20% tkhkh v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkhkh v dd + 1.0 v 50% v dd v il
capacitance o c, f = 1 mh z , v dd parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf clock capacitance c clk v in = 0 v 5 6 pf note: this parameter is sample tested. preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 20/29 ? 2005, gsi technology ac test conditions parameter conditions input high level 1.25 v input low level 0.25 v max. input slew rate 2 v/ns input reference level 0.75 v output reference level v ddq /2 note: test conditions as specified with output loading as shown unl ess otherwise noted. dq vt = v ddq /2 50 ? rq = 250 ? (hstl i/o) v ref = 0.75 v ac test load diagram input and output leakage characteristics parameter symbol test conditions min. max notes input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua doff i indoff v dd v in v il 0 v v in v il ?2 ua ?2 ua 2 ua 2 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua (t a = 25 = 1.8 v)
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 21/29 ? 2005, gsi technology programmable impedance hstl output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 1, 3 output low voltage v ol1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 2, 3 output high voltage v oh2 v ddq ? 0.2 v ddq v 4, 5 output low voltage v ol2 vss 0.2 v 4, 6 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 175 ? rq 350 ?). 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 175 ? rq 350 ?) . 3. parameter tested with rq = 250 ? and v ddq = 1.5 v or 1.8 v 4. minimum impedance mode, zq = v ss 5. i oh = ?1.0 ma 6. i ol = 1.0 ma operating currents parameter symbol test conditions -333 -300 -250 -200 -167 notes 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c operating current (x36): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2, 3 operating current (x18): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2, 3 operating current (x9): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2, 3 operating current (x8): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2, 3 standby current (nop): ddr i sb1 device deselected, i out = 0 ma, f = max, all inputs 0.2 v or v dd ? 0.2 v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 2, 4 notes: 1. power measured with output pins floating. 2. minimum cycle, i out = 0 ma 3. operating current is calculated wi th 50% read cycles and 50% write cycles. 4. standby current is only after all pending read and write burst operations are completed.
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 22/29 ? 2005, gsi technology ac electrical characteristics parameter symbol -333 -300 -250 -200 -167 units notes min max min max min max min max min max clock k, k clock cycle time c, c clock cycle time t khkh t chch 3.0 3.5 3.3 4.2 4.0 6.3 5.0 7.88 6.0 8.4 ns tkc variable t kcvar ? 0.2 ? 0.2 ? 0.2 ? 0.2 ? 0.2 ns 5 k, k clock high pulse width c, c clock high pulse width t khkl t chcl 1.2 ? 1.32 ? 1.6 ? 2.0 ? 2.4 ? ns k, k clock low pulse width c, c clock low pulse width t klkh t clch 1.2 ? 1.32 ? 1.6 ? 2.0 ? 2.4 ? ns k to k high c to c high t kh kh 1.35 ? 1.49 ? 1.8 ? 2.2 ? 2.7 ? ns k, k clock high to c, c clock high t khch 0 1.30 0 1.45 0 1.8 0 2.3 0 2.8 ns dll lock time t kclock 1024 ? 1024 ? 1024 ? 1024 ? 1024 ? cycle 6 k static to dll reset t kcreset 30 ? 30 ? 30 ? 30 ? 30 ? ns output times k, k clock high to data output valid c, c clock high to data output valid t khqv t chqv ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.5 ns 3 k, k clock high to data output hold c, c clock high to data output hold t khqx t chqx ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.5 ? ns 3 k, k clock high to echo clock valid c, c clock high to echo clock valid t khcqv t chcqv ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.5 ns k, k clock high to echo clock hold c, c clock high to echo clock hold t khcqx t chcqx ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.5 ? ns cq, cq high output valid t cqhqv ? 0.25 ? 0.27 ? 0.30 ? 0.35 ? 0.40 ns 7 cq, cq high output hold t cqhqx ?0.25 ? ?0.27 ? ?0.30 ? ?0.35 ? ?0.40 ? ns 7 k clock high to data output high-z c clock high to data output high-z t khqz t chqz ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.5 ns 3 k clock high to data output low-z c clock high to data output low-z t khqx1 t chqx1 ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.5 ? ns 3 setup times address input setup time t avkh 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns control input setup time t ivkh 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns 2 data input setup time t dvkh 0.28 ? 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 23/29 ? 2005, gsi technology hold times address input hold time t khax 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns control input hold time t khix 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns data input hold time t khdx 0.28 ? 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control singles are r , w , bw0 , bw1 , and ( nw0 , nw1 for x8) and ( bw2 , bw3 for x36). 3. if c, c are tied high, k, k become the references for c, c timing parameters 4. to avoid bus contention, at a given voltage and temperature tchq x1 is bigger than tchqz. the specs as shown do not imply bus contention because tchqx1 is a min param - eter that is worst case at totally different test conditions (0 c, 1.9 v) than tchqz, which is a max parameter (worst case at 70 c, 1.7 v). it is not possible for two srams on the same board to be at such different voltages and temperatures. 5. clock phase jitter is the variance from clock ri sing edge to the next expected clock rising edge. 6. v dd slew rate must be less than 0.1 v dc per 50 ns for dll lock retention. dll lock time begins once v dd and input clock are stable. 7. echo clock is very tightly controlled to data valid/data hold. by design, there is a 0.1 ns variation from echo clock to da ta. the datasheet parameters reflect tester guard bands and test setup variations. ac electrical character istics (continued) parameter symbol -333 -300 -250 -200 -167 units notes min max min max min max min max min max
k and k controlled read-write-read timing diagram read a write b nop write c read d write e nop a b c d e b b+1 b+2 b+3 c c+1 c+2 c+3 e e+1 b b+1 b+2 b+3 c c+1 c+2 c+3 e e+1 a a+1 a+2 a+3 d d+1 d+2 cqhqv khcqv khcqx cqhqx khcqv khcqx khqz khqx khqv khqx1 khdx dvkh khix ivkh khix ivkh khix ivkh avkh khkhbar klkhklkh khklkhkl khkhkhkh k k address r w bwx d q cq cq preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 24/29 ? 2005, gsi technology
c and c controlled read-write-read timing diagram read a nop read b write c nop write d nop a b c d c c+1 c+2 c+3 d d+1 d c c+1 c+2 c+3 d d+1 d a a+1 a+2 a+3 b b+1 b+2 b+3 cqhqv chcqx chcqx cqhqx chcqv chcqx chqz chqx chqv chqx1 dvkh khdx khix ivkh khix ivkh khix ivkh khax avkh khkhbar klkhklkh khklkhkl khkhkhkh k k address r w bwx d c c q cq cq preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 25/29 ? 2005, gsi technology
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 26/29 ? 2005, gsi technology package dimensions?165-bump fpbga (package e) a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 150.05 170.05 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.60 (165x) c seating plane 0.20 c 0.36~0.46 1.50 max.
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 27/29 ? 2005, gsi technology ordering information?gs i sigmaquad-ii sram org part number 1 type package speed (mhz) t a 3 8m x 8 gs8662d08e-333 sigmaquad-ii sram 165-bump bga 333 c 8m x 8 gs8662d08e-300 sigmaquad-ii sram 165-bump bga 300 c 8m x 8 gs8662d08e-250 sigmaquad-ii sram 165-bump bga 250 c 8m x 8 gs8662d08e-200 sigmaquad-ii sram 165-bump bga 200 c 8m x 8 gs8662d08e-167 sigmaquad-ii sram 165-bump bga 167 c 8m x 8 gs8662d08e-333i sigmaquad-ii sram 165-bump bga 333 i 8m x 8 gs8662d08e-300i sigmaquad-ii sram 165-bump bga 300 i 8m x 8 gs8662d08e-250i sigmaquad-ii sram 165-bump bga 250 i 8m x 8 gs8662d08e-200i sigmaquad-ii sram 165-bump bga 200 i 8m x 8 gs8662d08e-167i sigmaquad-ii sram 165-bump bga 167 i 8m x 9 gs8662d09e-333 sigmaquad-ii sram 165-bump bga 333 c 8m x 9 gs8662d09e-300 sigmaquad-ii sram 165-bump bga 300 c 8m x 9 gs8662d09e-250 sigmaquad-ii sram 165-bump bga 250 c 8m x 9 gs8662d09e-200 sigmaquad-ii sram 165-bump bga 200 c 8m x 9 gs8662d09e-167 sigmaquad-ii sram 165-bump bga 167 c 8m x 9 gs8662d09e-333i sigmaquad-ii sram 165-bump bga 333 i 8m x 9 gs8662d09e-300i sigmaquad-ii sram 165-bump bga 300 i 8m x 9 gs8662d09e-250i sigmaquad-ii sram 165-bump bga 250 i 8m x 9 gs8662d09e-200i sigmaquad-ii sram 165-bump bga 200 i 8m x 9 gs8662d09e-167i sigmaquad-ii sram 165-bump bga 167 i 4m x 18 gs8662d18e-333 sigmaquad-ii sram 165-bump bga 333 c 4m x 18 gs8662d18e-300 sigmaquad-ii sram 165-bump bga 300 c 4m x 18 gs8662d18e-250 sigmaquad-ii sram 165-bump bga 250 c 4m x 18 gs8662d18e-200 sigmaquad-ii sram 165-bump bga 200 c 4m x 18 gs8662d18e-167 sigmaquad-ii sram 165-bump bga 167 c 4m x 18 gs8662d18e-333i sigmaquad-ii sram 165-bump bga 333 i 4m x 18 gs8662d18e-300i sigmaquad-ii sram 165-bump bga 300 i 4m x 18 gs8662d18e-250i sigmaquad-ii sram 165-bump bga 250 i 4m x 18 gs8662d18e-200i sigmaquad-ii sram 165-bump bga 200 i 4m x 18 gs8662d18e-167i sigmaquad-ii sram 165-bump bga 167 i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs866x36e- 300t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range.
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 28/29 ? 2005, gsi technology 2m x 36 gs8662d36e-333 sigmaquad-ii sram 165-bump bga 333 c 2m x 36 gs8662d36e-300 sigmaquad-ii sram 165-bump bga 300 c 2m x 36 gs8662d36e-250 sigmaquad-ii sram 165-bump bga 250 c 2m x 36 gs8662d36e-200 sigmaquad-ii sram 165-bump bga 200 c 2m x 36 gs8662d36e-167 sigmaquad-ii sram 165-bump bga 167 c 2m x 36 gs8662d36e-333i sigmaquad-ii sram 165-bump bga 333 i 2m x 36 gs8662d36e-300i sigmaquad-ii sram 165-bump bga 300 i 2m x 36 gs8662d36e-250i sigmaquad-ii sram 165-bump bga 250 i 2m x 36 gs8662d36e-200i sigmaquad-ii sram 165-bump bga 200 i 2m x 36 gs8662d36e-167i sigmaquad-ii sram 165-bump bga 167 i 8m x 8 gs8662d08e-333 sigmaquad-ii sram 165-bump bga 333 c 8m x 8 gs8662d08ge-300 sigmaquad-ii sram rohs-compliant 165-bump bga 300 c 8m x 8 gs8662d08ge-250 sigmaquad-ii sram rohs-compliant 165-bump bga 250 c 8m x 8 gs8662d08ge-200 sigmaquad-ii sram rohs-compliant 165-bump bga 200 c 8m x 8 gs8662d08ge-167 sigmaquad-ii sram rohs-compliant 165-bump bga 167 c 8m x 8 gs8662d08ge-333i sigmaquad-ii sram rohs-compliant 165-bump bga 333 i 8m x 8 gs8662d08ge-300i sigmaquad-ii sram rohs-compliant 165-bump bga 300 i 8m x 8 gs8662d08ge-250i sigmaquad-ii sram rohs-compliant 165-bump bga 250 i 8m x 8 gs8662d08ge-200i sigmaquad-ii sram rohs-compliant 165-bump bga 200 i 8m x 8 gs8662d08ge-167i sigmaquad-ii sram rohs-compliant 165-bump bga 167 i 8m x 9 gs8662d09ge-333 sigmaquad-ii sram rohs-compliant 165-bump bga 333 c 8m x 9 gs8662d09ge-300 sigmaquad-ii sram rohs-compliant 165-bump bga 300 c 8m x 9 gs8662d09ge-250 sigmaquad-ii sram rohs-compliant 165-bump bga 250 c 8m x 9 gs8662d09ge-200 sigmaquad-ii sram rohs-compliant 165-bump bga 200 c 8m x 9 gs8662d09ge-167 sigmaquad-ii sram rohs-compliant 165-bump bga 167 c 8m x 9 gs8662d09ge-333i sigmaquad-ii sram rohs-compliant 165-bump bga 333 i 8m x 9 gs8662d09ge-300i sigmaquad-ii sram rohs-compliant 165-bump bga 300 i 8m x 9 gs8662d09ge-250i sigmaquad-ii sram rohs-compliant 165-bump bga 250 i 8m x 9 gs8662d09ge-200i sigmaquad-ii sram rohs-compliant 165-bump bga 200 i 8m x 9 gs8662d09ge-167i sigmaquad-ii sram rohs-compliant 165-bump bga 167 i ordering information?gs i sigmaquad-ii sram org part number 1 type package speed (mhz) t a 3 notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs866x36e- 300t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range.
preliminary gs8662d08/09/18/36e -333/300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 2/2006 29/29 ? 2005, gsi technology 4m x 18 gs8662d18ge-333 sigmaquad-ii sram rohs-compliant 165-bump bga 333 c 4m x 18 gs8662d18ge-300 sigmaquad-ii sram rohs-compliant 165-bump bga 300 c 4m x 18 gs8662d18ge-250 sigmaquad-ii sram rohs-compliant 165-bump bga 250 c 4m x 18 gs8662d18ge-200 sigmaquad-ii sram rohs-compliant 165-bump bga 200 c 4m x 18 gs8662d18ge-167 sigmaquad-ii sram rohs-compliant 165-bump bga 167 c 4m x 18 gs8662d18ge-333i sigmaquad-ii sram rohs-compliant 165-bump bga 333 i 4m x 18 gs8662d18ge-300i sigmaquad-ii sram rohs-compliant 165-bump bga 300 i 4m x 18 gs8662d18ge-250i sigmaquad-ii sram rohs-compliant 165-bump bga 250 i 4m x 18 gs8662d18ge-200i sigmaquad-ii sram rohs-compliant 165-bump bga 200 i 4m x 18 gs8662d18ge-167i sigmaquad-ii sram rohs-compliant 165-bump bga 167 i 2m x 36 gs8662d36ge-333 sigmaquad-ii sram rohs-compliant 165-bump bga 333 c 2m x 36 gs8662d36ge-300 sigmaquad-ii sram rohs-compliant 165-bump bga 300 c 2m x 36 gs8662d36ge-250 sigmaquad-ii sram rohs-compliant 165-bump bga 250 c 2m x 36 gs8662d36ge-200 sigmaquad-ii sram rohs-compliant 165-bump bga 200 c 2m x 36 gs8662d36ge-167 sigmaquad-ii sram rohs-compliant 165-bump bga 167 c 2m x 36 gs8662d36ge-333i sigmaquad-ii sram rohs-compliant 165-bump bga 333 i 2m x 36 gs8662d36ge-300i sigmaquad-ii sram rohs-compliant 165-bump bga 300 i 2m x 36 gs8662d36ge-250i sigmaquad-ii sram rohs-compliant 165-bump bga 250 i 2m x 36 gs8662d36ge-200i sigmaquad-ii sram rohs-compliant 165-bump bga 200 i 2m x 36 gs8662d36ge-167i sigmaquad-ii sram rohs-compliant 165-bump bga 167 i ordering information?gs i sigmaquad-ii sram org part number 1 type package speed (mhz) t a 3 notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs866x36e- 300t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range.

▲Up To Search▲

Price & Availability of GS8662D08E-XXX

	To Download GS8662D08E-XXX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .